The present invention relates to integrated circuit structures and, more particularly, to dielectric isolation, i.e., isolation with electrically insulative materials in integrated circuit structures.
The form of most existing integrated circuits is the so-called monolithic form. Such a structure contains great numbers of active and passive devices in a block or monolith of semiconductor material. Electrical connections between these active and passive devices are generally made on a surface of the semiconductor block of material. Until the present, junction isolation has been by far the most widely practiced manner of isolating devices or circuits in the integrated circuit from each other. For example, active P-type diffusions are customarily used to isolate conventional and P-N bipolar devices from one another and from other devices such as the resistors and capacitors. Such junction isolation is also used in integrated circuits utilizing field effect transistor devices. More detailed descriptions of junction isolation may be found in U.S. Pat. Nos. 3,319,311; 3,451,866; 3,508,209 and 3,539,876.
Although junction isolation has provided excellent electrical isolation in integrated circuits which have functioned very effectively over the years, at the present stage of the development of the integrated circuit art, there is an increasing demand in the field of digital integrated circuits for faster switching circuits. It has long been recognized that the capacitive effect of the isolating P-N junctions has a slowing effect on the switching speed of the integrated circuits. Up to now, the switching demands of the integrated circuits have been of a sufficiently low frequency that the capacitive effect in junction isolation has presented no major problems. However, with the higher frequency switching demand which can be expected in the field in the future, the capacitive effect produced by junction isolation may be an increasing problem. In addition, junction isolation requires relatively low device densities which is contrary to higher device densities required in large scale integration. Junction isolation also tends to give rise to parasitic transistor effects between the isolation region and its two abutting regions. Consequently, in recent years there has been a revival of interest in integrated circuits having dielectric isolation instead of junction isolation. In such dielectrically isolated circuits, the semiconductor devices are isolated from each other by insulative dielectric materials.
Conventionally, such dielectric isolation in integrated circuits has been formed by etching channels in a semiconductor member corresponding to the isolation regions. Usually a composite of a thin dielectric layer forming the interface with the semiconductor member covered by a thicker layer of polycrystalline silicon is deposited. Then, the other surface of the semiconductor member is either mechanically ground down or chemically etched until the bottom portions of the previously etched channels are reached. This leaves the structure wherein a plurality of pockets of semiconductor material surrounded by the dielectric layer are supported on the polycrystalline silicon substrate and separated from each other by extensions or fingers of the polycrystalline substrate. Such structures have been described in the prior art in patents such as U.S. Pat. Nos. 3,391,023; 3,332,137; 3,419,956; 3,372,063; 3,575,740; 3,421,205; 3,423,258; 3,423,255 and 3,478,418.
Complete dielectric isolation, as set forth in the prior art presented by the referenced patents, has had several shortcomings which have prevented it from being fully successful in high speed circuitry where it was particularly needed. Such high speed circuitry requires particularly shallow devices. Thus, the semiconductor pockets were required to be in the order of 0.1 mil thickness. However, because of wafer handling requirements in semiconductor integrated circuit fabrication techniques, the substrates which had to be etched or ground down were in the order of 6 to 8 mils in thickness. In practicing this prior art, fabricators experienced considerable difficulty in grinding, lapping or etching from 6 to 8 mils of material through a substrate with no inaccuracies which would affect the 0.1 mil pockets.
Recent work in the art has offered solutions to the problem of removal of the major portion of the semiconductor member to leave the semiconductor pockets. In accordance with the publication "Application of Preferential Electrochemical Etching of Silicon to Semiconductor Device Technology", M. Theunissen et al., Journal of the Electrochemical Society, July 1970, pp. 959- 965, selective anodic electrochemical etching may be used to remove and, thereby, cleanly and accurately separate the major portion of the semiconductor member from the semiconductor pockets in which the devices are to be formed. Copending application Ser. No. 340,150, Magdo et al., filed Mar. 12, 1973, U.S. Pat. No. 3,944,447, presents a related solution to this problem.
The present invention provides a different approach to this problem which avoids the necessity of utilizing the anodic electrochemical etch differentials between differently doped regions of semiconductor material in the removal of the major portion of the semiconductor member.
In order to form an integrated circuit structure with full dielectric isolation, the present invention uses ion bombardment. U.S. Pat. No. 3,622,382 and the publication "Epitaxial Silicon Layers Grown on Ion Implanted Silicon Layers", R. J. Dexter et al., Applied Physics Letters, Vol. 23, No. 8, Oct. 15, 1973, pp. 455- 457, described techniques for forming dielectrically isolated integrated circuits by the introduction into a silicon substrate of reactive impurities such as nitrogen, oxygen and carbon, and heating the same for a time sufficient to react such impurities with silicon to form a buried or subsurface layer of dielectric or insulative material while the silicon above this buried layer remains substantially monocrystalline. The publication further discloses that by implanting nitrogen a buried dielectric silicon nitride region may be formed slightly below the silicon surface without affecting the substantially monocrystalline nature of the silicon material above this buried region even to the extent that a monocrystalline epitaxial silicon layer may be formed about this surface. In accordance with the techniques described in this prior art, lateral dielectric isolation may be similarly achieved by forming dielectric regions of the same composition by ion bombardment extending from the buried regions to the surface of either the silicon substrate or the silicon epitaxial layer. In such structures, the buried region serves as part of the final dielectric isolation in the integrated circuit.
While the techniques described for forming such buried dielectric isolation are useful for many purposes, utilization for integrated circuits having very strict vertical tolerances is limited because it is difficult to consistently control the thickness of the dielectric material forming the buried region, the uniformity of the dielectric material within the buried region or the quality of the interface between the dielectric material and the silicon. This is particularly true when the techniques are utilized to form relatively thick dielectric regions in the order of at least one micron which would be desirable because of the relatively low parasitic capacitances in the resulting integrated circuits.